1. Field of the Invention
The present invention relates to a SOI (silicon on insulator) single crystalline chip structure, and more particularly, to a SOI single crystalline chip structure incorporating at least two different silicon layer thicknesses therein.
2. Description of the Prior Art
Reference is made to FIG. 1, a schematic, cross-sectional view of a SOI single crystalline chip structure 10 according to the prior art. A SOI single crystalline chip structure, by definition, has a silicon-based active device layer on an insulator, such as a silicon oxide. The SOI single crystalline chip structure 10 includes an active device layer 12 for placing at least one SOI device thereon, an insulating layer 14 below the active device layer 12, and a ground layer 16 below the insulating layer 14. In general, the thickness of the active device layer d1 is uniform, indicating that this prior art SOI chip structure 10 is a single-thickness active layer SOI chip structure. The insulating layer 14 is always provided with a buried oxide layer (BOX), which is formed in a variety of ways, such as ion-implanting oxygen ions into the silicon target, and then placing the silicon target into a relatively high temperature environment, in order to form this BOX at the predetermined depth of the silicon target. As for the active device layer 12, d1 ranges between 0.03 and 10 micrometers.
However, as SOC (system on a chip) has gradually become the mainstream product in today's market, the same active device layer of the chip structure should be able to accommodate different types of SOI devices placed thereon. Each such SOI device may have its own characteristics such as size, dissipation requirement, operating current, or voltage demand, and an SOI chip structure only with a uniform silicon layer thickness thus encounters difficulty in satisfying all SOI devices. In other words, some SOI devices with higher operating voltages/currents and more heat dissipation preferably should be placed on a thicker silicon layer, while SOI devices with smaller operating voltages or less heat dissipation requirement somewhere on the active device layer without that thickness for former SOI devices is no problem. Even with a uniformly thick active device layer, the prior art SOI chip structure is still available when it comes to the placement of SOI devices with higher heat dissipation requirement or greater operating voltages, as long as each of them occupies a comparatively larger area, in order to avoid any potential malfunction due to its stricter demands. As the result, the amount of SOI device placement for any given single chip structure is lowered accordingly, which is not economically efficient. Besides, the resistance to electro static discharge (ESD) of SOI chip structure 10 is undermined given that the active layer 12 is not effectively grounded and the breakdown voltage for SOI devices is limited due to the uniform silicon layer thickness d1.